1. Field of the Invention
The present invention relates to a technique for decoding coded data.
2. Description of the Related Art
Proposals for speeding up decoding processing of variable length coded data have been made. As one of these proposals, a proposal which comprises a normal symbol decoder and a decoder for specific symbols having high frequencies of occurrence, and simultaneously decodes two symbols when a codeword hits a specific symbol is available (for example, Japanese Patent Laid-Open No. 2003-174365). According to this technique, a maximum of two symbols can be decoded per clock cycle.
Also, the following variable length decoder has been proposed (Japanese Patent Laid-Open No. 9-284142). With this decoder, tables and barrel shifters in a number as large as the number of bits of a maximum code length are prepared, and one decode symbol is selected from outputs as many as the number of bits of a longest codeword to skip feedback from a Huffman decoder to the barrel shifters, thus assuring a high-speed operation.
With the aforementioned related art, when a codeword hits a specific symbol, two symbols can be decoded per clock cycle to achieve a high throughput, as described above. However, when a codeword does not hit, only one symbol can be decoded per clock cycle, and a high throughput cannot always be achieved. In variable length coding such as a Huffman decoder of JPEG, the coding speed depends on a code size, and a decode speed of a predetermined unit cannot be guaranteed in the related art.
In the related art, the numbers of tables and barrel shifters are as very large as the number of bits of a maximum code length, resulting in an increase in circuit scale. In order to achieve a high throughput, a plurality of symbols have to be simultaneously decoded. However, in order to simultaneously decode a plurality of symbols, the number of bits of the maximum code length increases to multiples of the number of symbols to be simultaneously decoded, and the number of tables required to simultaneously decode a plurality of symbols increases to a value corresponding to the number of symbols to the (number of symbols to be simultaneously decoded)-th power, thus considerably increasing the circuit scale.